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Started by Ufopolitics, May 19, 2024, 01:41 PM

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Quote from: rakarskiy on May 20, 2024, 01:15 AMCongratulations UFOpolitics!

I've been waiting a long time for you to move from mechanical commutator to electronic control. I did not want to impose the opinion that mechanics is no more than a proof of concept.

Hello Rakarskiy,

And thanks!

However, I disagree that mechanical is only for proving of concept...Brushed Motors, for example, have been on the market for a very long time, even after many other motor's methods have come up, still brushed motors has prevailed as having faster response, better torque, etc.
Mechanical switching is very reliable, and as a matter of fact, there are "things" that electronics can NOT do on this simple type of switching, for example, being able to Overlap between contacts plus regulate these overlapping gaps.

Quote from: rakarskiy on May 20, 2024, 01:15 AMI also already had the experience of developing a cascade of coils for a pulse device, on very simple elements. I only came to the question of power switches of the PNP transition.I encountered another problem, it is the reverse EMF at the moment of disconnection of the coil. If shunted with a diode, it greatly affects the collector (output) circuit EMF. If you put a simple snubber (RC), the reverse pulse voltage exceeding the transistor's capability kills it (your transistor has 100V limit). Under load there are no surges, but at idle or sudden change of load there may be trouble.You may not have large inductances and voltage spikes, just be aware that there is such a problem.

You have written it yourself above...the electronic switching has all those disadvantages, it will NOT happen with a Comm-Brush scenario.

Now, remember that on this new design, ALL COILS ARE IN SERIES, therefore, there is NEVER a FULL DISCONNECTION whenever swapping contacts, because coil behind (is never "disconnected") is still connected to the COIL'S SERIES CHAIN, behind AND in front.
A Parallel Connection of all coils would definitely be a FET killer by BEMF, BUT this is not the case here.

Quote from: rakarskiy on May 20, 2024, 01:15 AMOnce again congratulations on taking it to the next level.

Thanks, so far I believe this type of Dual Switching is designed very robust, and of course, it also depends on the Capacity of the MOSFET'S you are using.
We can add FET'S there that can handle up to 600V and up to 15-20 Amps, and still be Ultrafast switchers.

Now, do you remember a Test I made and uploaded a video about it, where I am capturing all the Energy generated by Self-Induction from the Exciter Coils?
Once you do that, ALL the BEMF is transferred to another circuit, where it can be stored and reused...
As, by doing this, we are diminishing all "kickback" BEMF from coils reversals.


Principles for the Development of a Complete Mind:Study the science of art. Study the art of science.
Develop your senses- especially learn how to see. Realize that everything connects to everything else.
―Leonardo da Vinci


Quote from: Ufopolitics on May 20, 2024, 11:28 AM...and as a matter of fact, there are "things" that electronics can NOT do on this simple type of switching, for example, being able to Overlap between contacts plus regulate these overlapping gaps.

Hello All,

On my previous post, I was citing what "apparently" cannot be done in Electronics-Solid State Drivers, like it was not being able to overlap signals and regulate them.

Well, this was due to a long exchange of emails with Member Kampen, and I agree to just leave it without the overlapping, since it was too complicated to achieve it.

But Kampen wanted to make the Design "PERFECT", without anything left, just yesterday I received this email from him:


Good afternoon Ufopolitics,

I am sending this email:

The NEW Commutator LOGIC Diagram-Schematics with Overlapping Timing and explanation.

SS-Commutator Overlapped Timing appears to be a specific concept within the realm of VLSI (Very-Large-Scale Integration) design, particularly relevant to the timing analysis and optimization of synchronous sequential circuits.

Although "SS-Commutator Overlapped Timing" might not be a standard term broadly recognized in literature, it likely relates to advanced techniques used to manage and optimize the timing of signals in complex digital circuits.

Breakdown of the Concept

1. SS (Synchronous Sequential) Circuits: These circuits use a clock signal to coordinate the changes in state. They include sequential elements (like flip-flops) and combinational logic that require precise timing to ensure correct operation.

2. Commutator: In a broader sense, a commutator refers to a device that periodically reverses the direction of current in an electric circuit. In the context of VLSI and timing, it might imply a mechanism or methodology that dynamically adjusts or shifts timing paths or phases within a circuit.

3. Overlapped Timing: This involves the strategic overlapping of timing windows to improve the efficiency of operations within a clock cycle. Overlapped timing helps in utilizing the clock cycle more effectively by allowing multiple operations to occur simultaneously without causing timing violations.

Understanding SS-Commutator Overlapped Timing

In VLSI design, managing the timing of synchronous sequential circuits is critical for achieving high performance and reliability. SS-Commutator Overlapped Timing can be understood as follows:

Dynamic Timing Adjustments: The concept of a "commutator" suggests dynamic adjustments in timing paths or phases. This could involve techniques where certain signals or operations are shifted within the clock cycle to optimize performance and meet timing constraints.

Efficiency in Clock Cycles: By overlapping timing windows, designers can ensure that multiple operations can be valid within the same clock cycle, thereby improving the throughput and efficiency of the circuit.

Managing Setup and Hold Times: Setup time is the period before the clock edge during which data must be stable, and hold time is the period after the clock edge during which data must remain stable.
Overlapping timing windows can help manage these constraints more effectively by allowing a buffer period for different operations.

Timing Analysis Tools: Tools like Static Timing Analysis (STA) are essential for evaluating the timing of circuits. Overlapped timing must be carefully analyzed to ensure that all signal paths meet the required setup and hold times, avoiding timing violations.

Practical Implications in Design

Increased Throughput: Proper management of overlapped timing can lead to higher throughput as more operations are completed within a given period. This is crucial for high-speed digital systems.

Power Efficiency: Optimized timing can allow the circuit to operate at lower frequencies while maintaining performance, leading to reduced power consumption.

Design Complexity: Implementing SS-Commutator Overlapped Timing can add complexity to the design process, requiring sophisticated techniques and careful analysis. However, the payoff is a more efficient and reliable circuit.

Advanced Optimization Techniques: Techniques such as clock skew management, retiming, pipelining, and dynamic timing adjustments are employed to achieve effective overlapped timing. These techniques help in distributing the timing load more evenly across the circuit.

SS-Commutator Overlapped Timing is an advanced concept in VLSI design focused on optimizing the timing of synchronous sequential circuits.
It involves dynamically adjusting timing paths and overlapping timing windows to maximize the efficiency and performance of the circuit.
By carefully managing setup and hold times and using sophisticated timing analysis tools, designers can create high-performance, power-efficient digital systems.

See attachment: Diagram_Cmos-Logic overlap Vers.01. PDf file.

Diagram_Cmos-Logic overlap_FF_Vers.png

Enjoy and Have a nice day.

Greetings, Alex


So, Alex achieved it!!

He did NOT give up!!, and kept testing and developing to reach the overlapping of Dual (Positive-Negative Signals at Unison)...adding the Clocks Chips plus all the needed components to achieve and regulate overlapping percentage:
The Logic Board had to be redesigned from scratch, as also some modification to the Switching FET Boards:



Regards to All


Principles for the Development of a Complete Mind:Study the science of art. Study the art of science.
Develop your senses- especially learn how to see. Realize that everything connects to everything else.
―Leonardo da Vinci


Hello All,

Ok so here Member Kamper is done with the Boards Design and Modeling of the whole Driver including the Overlap Function.

These Overlap Control (Potentiometer) would be on the CMOS Logic Board, and it can turn completely OFF (Zero overlap) or drive it all the way to 25%.

On this new Logic Control Board there would be two separate outputs to FET Boards, 8 pins for the NFET's Board and 8 pins for PFET's Board.



NFET_PCB_ Overlapped_Version.jpg



Member Kampen is doing an awesome job!!

Let's Congratulate him!!

Regards to All


Principles for the Development of a Complete Mind:Study the science of art. Study the art of science.
Develop your senses- especially learn how to see. Realize that everything connects to everything else.
―Leonardo da Vinci


Thank you Kampen and UFO for your work!

I want to make your driver. Can you upload schematic diagram, parts list and PCB schematic?

Thank you!



@ All,

This Solid State Overlapping Timing PCB is under development.
These 3 PCBs are prototypes that need now to be produced and assembled then functionality testing the Input and Output as required needs to monitor the timing signals and ensure they overlap as intended.

Then it will be TESTED by Ufopolitics.

Once the Overlapping Timing PCBs have been tested and their functionality has been verified, they will be ready for availability.
By following these steps, we can effectively use pooling to order these Overlapping Timing PCBs,
fully assembled and electronically tested them.
This process ensures cost efficiency and timely production for all users.

Greetings, Alex

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