FIGUERA GENERATOR SEQUENTIAL DUAL (+/-) SOLID-STATE DRIVER DEVELOPMENT

[Ufopolitics]

Hello to All,


Thanks to the great Contribution (and Patience) from Member @kampen, we have finally arrived at the latest setup of a Solid-State Driver, specifically designed for the latest Figuera Generator,
based on Dual Simultaneous Switching (DSS) of Positive and Negative Exciter Coils Sequence.

We agree since the beginning to make a Driver that will be a "Plug and Play" design, meaning, no Microprocessors that would need to be programmed.

The Basic Principle starts from a Logic Board, powered by low voltage, low amperage (12V and mA), and conducting the Sequence that we need, 1 to 8 then 8 to 1.

Logic Board is based on NAND Gate Drivers and Sequential IC's.

Then, the Two Executing, Switching Boards, based on P-FET's and N-FET's, separately.

So, on the N-FET Board we Input to Source the Higher Voltage Negative DC to Coils.

As on the P-FET Board we Input to High Side Source, the Positive DC to the switching Coils.

Here is a very Basic Block Diagram of Driver, please, realize that the "Executing Board" is actually based on Two Boards, for P & N MOSFET'S, NOT specified here:

On this Topic, I will be showing all specific details about ALL Circuit Boards, Components Spec's required as also Boards Manufacture designs.

Regards

Ufopolitics

[Ufopolitics]

Hello All,

THE ELECTROMAGNETIC RELAY PRINCIPLE

This Method of switching is basically similar to the way an Electromagnetic Relay works:

With a very low Power Input, we energize a Coil that is wound with very fine wire and many turns, therefore its currents are very low.

However, once that a Magnetic Field is generated at center core, it attracts the Upper Contacts, CLOSING the Higher Voltage, Higher Amperage of the two Right Contacts.

The setback of a Relay, is that at higher frequencies, it may not have the Fast Switching Response Properties as an Electronic Solid State MOSFET Transistor would have.

And we need here to be able to drive at frequencies that go from 50 to 100 Hertz.


Regards


Ufopolitics

[Ufopolitics]

THE SIGNALS ANALYSIS

EDIT: Please do NOT misinterpret the Red Signals in an ESCALATING GRAPHIC AS they "WOULD BE" on an INCREASE-DECREASE of Power!!

ALL SIGNALS CARRY THE SAME POWER (V&A) AT ALL TIMES!!, LIKE IS SHOWN A FLAT RED LINE ON RIGHT IMAGES OF POWER VERSUS SIGNALS SEQUENCE

Hello,

Ok, here I want to show the True Signals we are achieving with this DSS Driver:

We will be able to regulate Frequency (speed) from Zero to 100 Hz, as also the Duty Cycle, HOWEVER, I highly recommend running at 100% Duty Cycle (No Time OFF on each signal)

As represented on Graphic above.

However, each Sequential Signal, would collapse straight down, on a vertical line (zero time off), as soon as next signal is turned ON, like shown on image below:

Same way that turning ON each signal, would also be in a Vertical Line (instant ON)

So, this part is NOT the same way that Commutator-Brush Switching works, where there is always an "Overlapped" Time in between signals, when Brush is switching from a contact to the next, there is ALWAYS a "Make Before Brake"...:

However, at higher speeds Switching, this slight difference is almost not noticeable, if we are running at 100% Duty Cycle.
Plus, remember ALL Sequential Exciter Coils are in SERIES CONNECTIONS between ALL of them, so, it will NEVER be a collapsing, like in a Parallel Connection would take place.

Regards

Ufopolitics

[Ufopolitics]

CIRCUIT BOARDS SCHEMATICS (VERSION 1)

Hello All,

Ok, first, All Logic Sequential Circuit running to Higher Voltage at MOSFET Boards (Both, P & N FETS) are Protected by OPTO-COUPLERS.

This is done to protect Logic Board sensitive components at the event of a short circuit taking place at any of the MOSFET's terminals, basically shorting Gates with Source or Drain, whenever dielectric insulation melts, resulting in a full short circuit.

LOGIC BOARD SCHEMATIC (VERSION 1)

N-FET CIRCUIT SCHEMATIC (VERSION 1)

P-FET CIRCUIT SCHEMATIC (VERSION 1)

CIRCUIT BOARDS DESIGN AND CONNECTIONS (VERSION 1)

Ufopolitics

[Ufopolitics]

Hello to All,

Ok, as you have all noticed, the Logic Board Out Terminal (15 Pins) Sends its Switching Signals (1-8/8-1) to BOTH MOSFET (P & N) Boards.

This means that Both, P-FETs and N-FETs would be receiving the same EXECUTION SIGNAL to each Gate in the Sequence, and this design guarantees a perfect UNISON Contact for all Positive and Negative terminals of our Exciting Coils.

At the same token, ALL Regulation Controls (PWM/FREQ) are at the Logic Board, so, when we regulate speed (Hz), it will be evenly distributed to the High (+) and Low (-) Sides perfectly at UNISON.
This way we will never have a Coil on the sequence left without powering it.

It took a very long thread of emails exchange to reach this final design between Kamper and me, as I was trying to duplicate the Mechanical Switching Properties, as close as Solid-State Electronics Switching would allow.

We started the first designs with the Single Switching Schematics, where only Positive is being switched, until I came up with the Dual Switching design, so, we (Kamper and I) had to start from scratch again...

The work done by Member Kamper and his Team at the Netherlands is amazingly well done!!

Now He is in the process of ordering all components and order the Circuit Boards to be printed.


Regards


Ufopolitics