FIGUERA'S AETHER MAGNETIC FIELDS LINEAR PUMP, REVIVED

[kampen]

Hello everyone,

I would like to share this diagram, which illustrates 
the core operating principle of the Solid-State Switching (SSD) system for the 15-coil linear chain.
The image below shows how the magnetic field is translated along the coil chain using a controlled switching sequence.

1. INITIAL STATE (G3)

• Active selectors: SL2 + SR10
• Energized coils: Q3 → Q10 (8 coils)

In this state:

• The current enters at node N2 and exits at N10
• A stable current path is established
• The magnetic field is formed across these 8 coils
• This defines the active window

 
2. TRANSITION (MAKE-BEFORE-BREAK)

• Active selectors: SL2 + SL3 + SR10 + SR11
• Energized coils: Q3 → Q11 (temporary 9 coils)

This is the critical step:

• The next selectors are turned ON before the previous ones are turned OFF
• This creates a short overlap condition
• During this moment:
  
  • Current flows through both paths
  • There is no interruption
  • The magnetic field remains continuous

⚠️ This is NOT a steady state only a brief transition.
 
3. FINAL STATE (G4)

• Active selectors: SL3 + SR11
• Energized coils: Q4 → Q11 (8 coils)

Now:

• The window has shifted by one coil to the right
• A new stable current path is established
• The system is ready for the next step

 
KEY PRINCIPLE
👉 Make-Before-Break Switching
Always:

• Turn ON the next selectors before
• Turning OFF the previous selectors

This ensures:

• Continuous current flow
• No "dead time"
• No magnetic field collapse
• Smooth field translation

 
What this means in practice
This sequence is essentially a solid-state commutator, where:

• The active magnetic field is not rotating mechanically
• It is translated electronically
• Coil by coil, step by step

The smoother and more synchronized this transition is, 
the more stable and efficient the system becomes.
 
If anyone has questions or sees improvements, feel free to comment always good to refine this together.

Regards, Alex

[kampen]

Hello everyone,

I would like to explain this timing diagram, 
which helps visualize the relationship between the SSD gate signals and the resulting current continuity during switching.

What this diagram shows
This graph represents:

• Gate signals of two switching elements (for example, SL and SR transitions)
• Their timing relationship over a switching cycle
• The effect on current continuity

 
Understanding the lines

• Red line → represents the previous active selector (turning OFF)
• Green line → represents the next selector (turning ON)
• Top flat line (~1 level) → represents the current path remaining continuous

 
Key observation
Between time ≈ 4 and time ≈ 6, both signals are active:

• The red signal has not yet turned OFF
• The green signal has already turned ON

👉 This creates an overlap region
 
Why this is important
This overlap demonstrates the Make-Before-Break principle:

• The next path is established before the previous one is removed
• This prevents:
  
  • Current interruption
  • Magnetic field collapse
  • Voltage spikes (inductive kickback)

As a result:

• The current remains stable and continuous
• The magnetic field is smoothly transferred from one coil group to the next

 
What would happen without overlap?
If the signals were switched with a gap (Break-Before-Make):

• Current would drop to zero momentarily
• The magnetic field would collapse
• You would introduce:
  
  • Instability
  • Energy losses
  • Potential stress on components

 
Practical takeaway
For the SSD system:
👉 Proper timing control is just as important as the wiring itself

• Even perfectly wired hardware will not perform correctly
• If the timing does not enforce this overlap behavior

 
This diagram is a simple but important representation 
of how we achieve smooth field translation in a fully solid-state system.

Feel free to comment or suggest refinements.

Regards, Alex

[Ufopolitics]

Hello dear friend @kampen ,

Everything looks clean and clear based on all your detailed work displayed here!!

One thing that I have still 'pending' to finally have a full grip on the whole SSD Setup:

The Selectors (SL# & SR#) work in PAIRS for each Group, and always be like that.
These Selectors are in charge to turn ON and OFF on the sequencing order.

Now, you have mentioned to use Back to Back NFET's on a BIPOLAR arrangement, (which is GREAT!) where:

• Each Bipolar switch have a Common (1) Gate Trigger.
• Which means that on the Logic Board you will only need Eight [8] Gate Triggers Terminals to the Eight [8] Bipolar Switches.

• Now are these 'Selectors' the Bipolar Switches Circuit?
• Or the Bipolar Switches Trigger the Selectors?

Sorry I may have 'jumped the gun' here...as it maybe some further circuits -not presented yet- where ALL these components would be shown on their orderly connections.

Either way by using Bipolar Switches here is a GREAT Advantage given the use of ALL same NFET's with exactly same characteristics which generates a very Robust Switching Network.
As it will also simplify the Logic Board to a more reduced number (50%) of connections to trigger only eight Gates for just Eight Bipolar Switches than all previous Logic Boards.

Using a Single Gate Trigger for Two NFET Switches also guarantees a PERFECTLY UNISON switching.

Then, my only doubt here relates to Selectors and Bipolar Switches...

• You will have Selectors PLUS Bipolar Switches? where Bipolar Switches turn Selectors ON and OFF?
• Or are each Selector Pair a FULL CIRCUIT which comprehends its Bipolar Switches?

Please feel free to correct any of my assumptions here!

Thanks in advance!

Regards

Ufopolitics

[kampen]

Reply to Message # 707
Hello, my dear friend Ufopolitics,

Excellent question, and you are very close. 
I think the only confusion is the naming.
The selectors are the bipolar/bidirectional MOSFET switch circuits.

So there is not:
Selector PLUS bipolar switch
Instead:
Each selector IS one bidirectional solid-state switch.
In other words:

• SL0 is one bidirectional MOSFET selector
• SL1 is one bidirectional MOSFET selector
• ...
• SR15 is one bidirectional MOSFET selector

Each selector is made from:

• two back-to-back NFETs
• one common gate-drive command
• one isolated/floating gate driver channel

So yes, one selector circuit contains the two NFETs.
The full system therefore, has:

• 16 selectors total
• 8 left selectors: SL0–SL7
• 8 right selectors: SR8–SR15
• each selector = 2 NFETs
• total = 32 NFETs

Now, the selectors operate in logical pairs to form a group:

• G1 = SL0 + SR8
• G2 = SL1 + SR9
• G3 = SL2 + SR10
• ...
• G8 = SL7 + SR15

So the "pair" is the active group command, 
but physically, it is still two selector circuits turning on together.

Important clarification:
Even though each group uses a pair, 
I would still prefer to keep 16 physical gate-driver channels available, 
not only 8, because we need accurate control during transitions.
For example, during G3 → G4:

• outgoing: SL2 + SR10
• incoming: SL3 + SR11

During overlap, all four are briefly active:

• SL2 + SL3 + SR10 + SR11

That is the make-before-break transition.

So the cleanest architecture is:

• each selector has its own gate-driver output
• FPGA controls all 16 selector commands
• FPGA logic ensures only legal group pairs and legal overlap states occur

It is possible for the FPGA logic to think in terms of 8 group commands, 
but at the hardware level, I still want the 16 selector outputs available. 
This gives more flexibility, better debugging, and safer timing control.

So to answer your question directly:
The selectors are the bidirectional MOSFET switch circuits.
 The back-to-back NFETs are inside each selector.
 The selector pairs form the active groups.

And yes, using all NFETs in this back-to-back arrangement is a very strong advantage:

• same device type
• same switching behavior
• bidirectional blocking
• no body-diode errors
• robust solid-state commutation

Your understanding is basically correct; the only correction is that we should not reduce 
the physical system to only 8 gate triggers unless we intentionally combine each SL/SR pair in hardware.
 
For best control, especially with overlap timing, I prefer 16 independently driven selector channels.

Regards, Alex

[kampen]

Hello everyone,

We have now reached a very important point in the project. 
We now have:

• ✔ Physical core + bobbins
• ✔ Winding specs and first coils
• ✔ Correct SSD topology
• ✔ Correct switching logic (make-before-break)

So the next step is not just "build more," it is to move into controlled validation and staged bring-up.

Let me outline this clearly.
NEXT STEP: Controlled SSD Prototype (Minimum Viable System)

Before building the full 15-coil system, we should:
👉 Build and validate a small-scale SSD switching section
Why?
Because:

• This system is timing-sensitive
• Mistakes can damage MOSFETs instantly
• Debugging 15 coils at once is very hard

 
Step 1 — Build a 3–4 Coil Test Section
Instead of 15 coils:
👉 Use 4 coils (Q1–Q4) with taps:

• N0 – N4
• Implement:
  
  • SL0, SL1
  • SR2, SR3

Goal:

• Reproduce one moving window transition
• Validate:
  
  • Current continuity
  • Switching timing
  • No voltage spikes

 
Step 2 — Build ONE SSD Channel Properly
Each selector (SL or SR) must be:
👉 Back-to-back MOSFET switch
Minimum design:

• 2x N-MOSFETs (source-to-source)
• Gate driver (isolated or high-side capable)

Why:

• Prevent body diode conduction
• Allow true bidirectional blocking

 
Step 3 — Gate Driver + Control (VERY IMPORTANT)
We now implement control logic:
👉 Start simple:

• Microcontroller (Arduino / STM32)
   OR
• FPGA (if you're ready)

First test logic:
Cycle:

Code Select Expand

State 1: SL0 + SR2

Code Select Expand

Transition: SL0 + SL1 + SR2 + SR3 (overlap)

Code Select Expand

State 2: SL1 + SR3
👉 Add dead-time control carefully reversed:

• Not dead time → but overlap time

 
Step 4 — Power Supply Strategy
Do NOT use a raw voltage supply initially.
👉 Use:

• Current-limited bench supply
• OR series resistor for first tests

Why:

• Protect MOSFETs
• Control inrush
• Avoid catastrophic failure

 
Step 5 — Measurement Setup
Before scaling, verify behavior:
Measure:

• Current waveform (scope)
• Voltage at nodes
• Switching transitions

What we want to see:
✔ No current drop during transition
 ✔ No large voltage spikes
 ✔ Smooth transfer of conduction path
 
Step 6 — Only THEN scale to 15 Coils
Once the 4-coil system is stable:
👉 Expand:

• 8 coils (full window)
• Then the full 15-coil chain

 
PARALLEL MECHANICAL STEP
While electronics are being validated:
✔ Continue winding all coils
 ✔ Keep all coils:

• Identical resistance
• Same polarity
• Same winding direction

👉 This is critical for field symmetry
 
CRITICAL RISKS (Be aware)
If you skip the staged approach:

• ❌ MOSFET shoot-through
• ❌ Inductive voltage spikes
• ❌ Unstable field behavior
• ❌ Hard-to-debug system

 
SIMPLE ROADMAP

• Small coil section (4 coils)
• One working SSD channel
• Controlled switching timing
• Verify current continuity
• Expand to the full chain
• Integrate full SSD banks

 
Key Insight
We are no longer building just a coil system.
👉 We are building:
A Synchronized Power Electronics + Magnetic System
That means:
Timing + Topology + Symmetry = SUCCESS
 
The next step I will give you:
✔ Exact MOSFET circuit per selector
 ✔ Gate driver schematic
 ✔ First Arduino / FPGA timing code
 ✔ Safe test procedure checklist

Regards, Alex